The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Apr. 07, 2020
Applicant:

Nippon Telegraph and Telephone Corporation, Tokyo, JP;

Inventors:

Naoki Terao, Tokyo, JP;

Munehiko Nagatani, Tokyo, JP;

Hideyuki Nosaka, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/00 (2006.01); H03M 1/12 (2006.01); G11C 27/02 (2006.01); H03K 5/003 (2006.01); H03K 5/24 (2006.01); H03K 17/60 (2006.01);
U.S. Cl.
CPC ...
H03M 1/124 (2013.01); G11C 27/02 (2013.01); H03K 5/003 (2013.01); H03K 5/24 (2013.01); H03K 17/60 (2013.01);
Abstract

Bias adjusting circuits (_(-),_) (where k is an integer equal to or greater than 1 and equal to or less than N, and N is an integer equal to or more than 2) adjust DC bias voltage of at least one of clock signals such that a duty ratio, which is a ratio between a period in which a clock signal is High as to a clock signal and a period in which the clock signal is Low thereasto, becomes (N−+1):(−1). Sampling circuits switch between a track mode in which an output signal tracks an input signal, and a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with clock signals output from the bias adjusting circuits (_to_N).


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