The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Nov. 15, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Akhilesh Yadav, Karnataka, IN;

Eldhose Peter, Karnataka, IN;

Rakesh Balakrishnan, Karnataka, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 29/52 (2006.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G06F 12/1045 (2016.01); G06F 13/16 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
G11C 7/106 (2013.01); G06F 12/1054 (2013.01); G06F 12/1063 (2013.01); G06F 13/1605 (2013.01); G11C 7/1039 (2013.01); G11C 7/1087 (2013.01); G11C 8/08 (2013.01); H03K 19/018521 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A storage device is provided that allows a controller to directly access bytes of data in data latches connected to memory, as opposed to through controller RAM. The storage device may include a memory, a plurality of data latches connected to the memory, and a controller coupled to each of the data latches. The controller is configured to access one or more bytes of decoded data in one or more of the data latches. For instance, the controller may provide a command including an address for data in the memory, and may process one or more bytes of the data in at least one of the data latches in response to the command. The controller may also store a mapping of addresses for each of the word lines, including the address provided in the command. As a result, operation latency may be reduced and controller RAM savings achieved.


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