The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Jun. 14, 2022
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Luigi Sole, Milan, IT;

Antonio Giordano, Milan, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/099 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
H03L 7/099 (2013.01); G06F 1/08 (2013.01); G06F 1/12 (2013.01);
Abstract

In an embodiment a timing system includes a master timing device including a master oscillator stage configured to receive a reference signal and to generate a first main clock signal frequency-locked with the reference signal, a master timing stage including a master counter configured to update value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter and a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses, and a slave timing device including a slave oscillator stage configured to receive the reference signal and to generate a second main clock signal frequency-locked with the reference signal, a slave timing stage and a slave synchronization stage.


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