The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

May. 13, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Troy Stockstad, Chandler, AZ (US);

Gianluca Valentino, San Diego, CA (US);

Ricardo Goncalves, Chandler, AZ (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/08 (2006.01); H02M 3/158 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 1/08 (2013.01); H02M 1/0006 (2021.05); H02M 3/158 (2013.01);
Abstract

Techniques and apparatus for driving a transistor gate of a switched-mode power supply (SMPS) circuit. One example gate driver for a switching transistor of an SMPS circuit generally includes a first power supply rail; a reference rail; an output node for coupling to a control input of the switching transistor; a floating supply node; a pulldown transistor having a drain coupled to the output node of the gate driver and having a source coupled to the reference rail; and a pulldown logic buffer having a first power supply input coupled to the floating supply node, having a second power supply input coupled to the reference rail, and having an output coupled to a gate of the pulldown transistor. The floating supply node is configured to selectively receive power from the first power supply rail and the output node of the gate driver.


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