The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Dec. 08, 2021
Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventors:

Mari Saji, Nagaokakyo, JP;

Atsushi Kurokawa, Nagaokakyo, JP;

Koshi Himeda, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/737 (2006.01); H01L 23/00 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/737 (2013.01); H01L 24/13 (2013.01); H01L 29/66242 (2013.01); H01L 29/66318 (2013.01); H01L 2224/0401 (2013.01);
Abstract

A semiconductor device includes a substrate having an upper surface on which are arranged first transistors each including a mesa structure formed of a semiconductor. A first bump having a shape elongated in one direction in plan view and connected to the first transistors is arranged at a position overlapping the first transistors in plan view. A second bump has a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump. A first metal pattern is arranged between the first and second bumps in plan view. When the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the first transistors and lower than a lower surface of the first bump.


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