The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Jan. 07, 2021
Applicant:

Globalfoundries Dresden Module One Limited Liability Company & Co. KG, Dresden, DE;

Inventors:

Stefan Dünkel, Dresden, DE;

Dominik M. Kleimaier, Dresden, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/118 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11807 (2013.01); H01L 29/6684 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7881 (2013.01); H01L 29/78391 (2014.09); H01L 29/792 (2013.01); H01L 2027/11866 (2013.01);
Abstract

Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).


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