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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11817389 B1

PDFFull Text
Date of Patent:
Nov. 14, 2023

Filed:

Mar. 24, 2020

Multi-metal interconnects for semiconductor device structures

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hsueh-Chung Chen, Cohoes, NY (US);

Chih-Chao Yang, Glenmont, NY (US);

Yann Mignot, Slingerlands, NY (US);

Shanti Pancharatnam, Albany, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Fleit Intellectual Property Law

Thomas Grzesik

Primary Examiner:

Duy T Nguyen

Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 23/532 (2006.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 50/10 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01); H01L 21/768 (2006.01); H10N 50/01 (2023.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/53209 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H10B 61/00 (2023.02); H10B 63/80 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02);
Abstract

A semiconductor device structure includes a memory element disposed within an interlayer dielectric (ILD) layer. A contact is disposed within the ILD in contact with the memory element and includes a first metal. A logic element is disposed within the ILD and comprises a second metal that is different than the first metal. A method of forming the semiconductor structure includes forming at least one memory element within an interlayer dielectric (ILD) layer. A contact that includes a first metal is formed in contact with the memory element. At least one logic element is formed in the ILD layer, where the logic element includes a second metal that is different than the first metal.

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