The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2023
Filed:
Jan. 06, 2021
Applicant:
Murata Manufacturing Co., Ltd., Kyoto, JP;
Inventors:
Kiyoshi Aikawa, Kyoto, JP;
Takafumi Kusuyama, Kyoto, JP;
Assignee:
MURATA MANUFACTURING CO., LTD., Kyoto, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01); H01L 25/065 (2023.01); H05K 3/28 (2006.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01); H01L 23/14 (2006.01);
U.S. Cl.
CPC ...
H01L 23/14 (2013.01); H01L 23/3107 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/66 (2013.01); H01L 25/18 (2013.01); H01L 2223/6688 (2013.01);
Abstract
A circuit module includes a first wiring substrate having a first main surface and a plurality of first components mounted on the first main surface. The plurality of first components includes a multilayer component formed as a single chip by being sealed using resin members. The multilayer component includes a second wiring substrate having a second main surface and a third main surface that face each other, a second component mounted on the second main surface, and a third component mounted on the third main surface.