The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Jun. 22, 2020
Applicants:

Hefei Boe Optoelectronics Technology Co., Ltd., Anhui, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Qing Yang, Beijing, CN;

Jiacheng Huang, Beijing, CN;

Gang Zhang, Beijing, CN;

Meng Zhang, Beijing, CN;

Lingling Liu, Beijing, CN;

Tingfei Wang, Beijing, CN;

Qiang Zhu, Beijing, CN;

Yunyun Zhang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G06F 3/041 (2006.01); G02F 1/1333 (2006.01); G02F 1/1345 (2006.01); G09G 3/20 (2006.01); G09G 3/32 (2016.01); G09G 3/36 (2006.01); H10K 50/844 (2023.01); H10K 50/86 (2023.01); H10K 59/40 (2023.01); G02F 1/1335 (2006.01);
U.S. Cl.
CPC ...
G06F 3/04184 (2019.05); G02F 1/1345 (2013.01); G02F 1/13338 (2013.01); G06F 3/0412 (2013.01); G09G 3/2096 (2013.01); G09G 3/32 (2013.01); G09G 3/3677 (2013.01); H10K 50/844 (2023.02); H10K 50/865 (2023.02); H10K 59/40 (2023.02); G02F 1/133512 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01);
Abstract

A timing controller includes: a field programmable gate array configured to generate a reference clock signal, and obtain at least one group of clock signals according to the reference clock signal. Each group of clock signals includes at least two clock signals, and a waveform of each clock signal is same as a waveform of the reference clock signal, and active levels in different clock signals are provided with a delay of a preset duration. The reference clock signal includes a first clock sub-signal for first duration and a second clock sub-signal for a second duration. At least one output interface group is connected to the field programmable gate array. Each output interface group includes at least two output interfaces, and each of the at least two output interfaces is configured to output one clock signal of a group of clock signals corresponding to the output interface group.


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