The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Mar. 27, 2017
Applicant:

Kyocera Corporation, Kyoto, JP;

Inventors:

Hiroyuki Nakamichi, Kirishima, JP;

Takayuki Shirasaki, Omihachiman, JP;

Assignee:

Kyocera Corporation, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/03 (2006.01); H01L 23/055 (2006.01); H05K 1/18 (2006.01); G02F 1/055 (2006.01);
U.S. Cl.
CPC ...
G02F 1/0305 (2013.01); H01L 23/055 (2013.01); H05K 1/18 (2013.01); H05K 1/189 (2013.01); G02F 1/055 (2013.01); H05K 2201/10121 (2013.01);
Abstract

A functional element housing package includes a pin terminal disposed in an outer region of a housing for housing a functional element. A wiring substrate is connected with the pin terminal. The wiring substrate includes a through hole for receiving the pin terminal, a first metallic layer disposed around an opening of the through hole on a side of the wiring substrate which side is located close to the housing, a second metallic layer disposed around an opening of the through hole on a side of the wiring substrate which is opposed to the side located close to the housing, the second metallic layer being greater in area than the first metallic layer, a connection wiring line connected to the first metallic layer or the second metallic layer, and a solder which connects the pin terminal to each of the first metallic layer and the second metallic layer.


Find Patent Forward Citations

Nakamichi, Hiroyuki. (2023). Functional element housing package, and semiconductor device and ln modulator (U.S. Patent No. 11815749). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11815749

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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