The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Dec. 27, 2022
Applicant:

Proteantecs Ltd., Haifa, IL;

Inventors:

Eyal Fayneh, Givatayim, IL;

Guy Redler, Haifa, IL;

Evelyn Landman, Haifa, IL;

Assignee:

PROTEANTECS LTD., Haifa, IL;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31725 (2013.01); G01R 31/2882 (2013.01);
Abstract

An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.


Find Patent Forward Citations

Loading…