The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Jun. 18, 2021
Applicant:

Bae Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);

Inventors:

Shailendra Srinivas, Nashua, NH (US);

Joseph D. Cali, Merrimack, NH (US);

Steven E. Turner, Nashua, NH (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/093 (2006.01); H03L 7/08 (2006.01); G06F 1/08 (2006.01); G06F 1/03 (2006.01); G06F 1/02 (2006.01); H04L 27/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/093 (2013.01); G06F 1/022 (2013.01); G06F 1/0321 (2013.01); G06F 1/08 (2013.01); H03L 7/08 (2013.01); H03L 2207/50 (2013.01); H04L 2027/0065 (2013.01); H04L 2027/0073 (2013.01);
Abstract

A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.


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