The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Aug. 31, 2022
Applicant:

Rolls-royce Deutschland Ltd & CO KG, Blankenfelde-Mahlow, DE;

Inventors:

Uwe Waltrich, Forchheim, DE;

Stanley Buchert, Herzogenaurach, DE;

Assignee:

Rolls-Royce Deutschland Ltd & Co KG, Blankenfelde-Mahlow, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02K 11/33 (2016.01); H01L 25/16 (2023.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/373 (2006.01); B64D 27/24 (2006.01); H05K 1/02 (2006.01); B64D 27/10 (2006.01); B64D 27/02 (2006.01);
U.S. Cl.
CPC ...
H02K 11/33 (2016.01); B64D 27/24 (2013.01); H01L 23/3121 (2013.01); H01L 23/3735 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 25/16 (2013.01); H05K 1/0209 (2013.01); B64D 27/10 (2013.01); B64D 2027/026 (2013.01); H02K 2211/03 (2013.01);
Abstract

A power electronics converter includes a multi-layer planar carrier substrate, and a converter commutation cell including a power circuit. The power circuit includes at least one power semiconductor switching element, each of which is comprised in a power semiconductor prepackage. Each power semiconductor prepackage includes one or more power semiconductor switching elements embedded in a solid insulating material. A heat sink is arranged to remove heat from the respective power semiconductor prepackage. A thermal interface layer is arranged between a heat removal side of the respective power semiconductor prepackage and the heat sink. The thermal interface layer has a thermal conductivity and a mechanical compressibility. A converter parameter, which is defined as the mechanical compressibility of the thermal interface layer divided by the thermal conductivity of the thermal interface layer, satisfies 0.1 MNK/Wm<Ω<1 GNK/Wm.


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