The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Oct. 31, 2022
Applicant:

Lextar Electronics Corporation, Hsinchu, TW;

Inventors:

Jih-Kang Chen, Hsinchu, TW;

Shih-Wei Yang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/14 (2010.01); H01L 33/46 (2010.01); H01L 33/52 (2010.01); H01L 33/32 (2010.01); H01L 33/38 (2010.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
H01L 33/145 (2013.01); H01L 33/46 (2013.01); H01L 33/52 (2013.01); H01L 33/0012 (2013.01); H01L 33/32 (2013.01); H01L 33/382 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0025 (2013.01);
Abstract

The forming method of a flip-chip light emitting diode structure includes the following steps. A first substrate including a first semiconductor layer, an active layer on the first semiconductor layer and a second semiconductor layer on the active layer is provided. A first current blocking layer is formed on the second semiconductor layer, in which the first current blocking layer has a plurality of interspaces. A reflective layer covering the interspaces is formed, in which the reflective layer has a plurality of recesses, and each of the recesses is corresponding to each of the interspaces. A second current blocking layer filling into the recesses is formed.


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