The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Feb. 28, 2022
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Hitoshi Okano, Kanagawa, JP;

Hiroyuki Kawashima, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/76843 (2013.01); H01L 23/528 (2013.01); H01L 28/60 (2013.01); H01L 21/76898 (2013.01); H01L 23/5226 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01);
Abstract

The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.


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