The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Jan. 12, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Rui Li, San Diego, CA (US);

De Lu, San Diego, CA (US);

Venkat Narayanan, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1009 (2013.01); G11C 7/1087 (2013.01);
Abstract

An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.


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