The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2023
Filed:
May. 19, 2022
Infineon Technologies Llc, San Jose, CA (US);
Krishnaswamy Ramkumar, San Jose, CA (US);
Venkatraman Prabhakar, Pleasanton, CA (US);
Vineet Agrawal, San Jose, CA (US);
Long Hinh, San Jose, CA (US);
Santanu Kumar Samanta, West Bengal, IN;
Ravindra Kapre, San Jose, CA (US);
Infineon Technologies LLC, San Jose, CA (US);
Abstract
A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.