The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Jul. 02, 2021
Applicant:

Shanghai Biren Technology Co., Ltd, Shanghai, CN;

Inventors:

Zhou Hong, Shanghai, CN;

YuFei Zhang;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 1/16 (2006.01); G06F 7/57 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 1/16 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/3802 (2013.01);
Abstract

The invention relates to an apparatus for vector computing incorporating with matrix multiply and accumulation (MMA) calculation. The apparatus includes a streaming multiprocessor (SM), and a block selector. The register space is divided into physical blocks, each of which includes register groups, and a general matrix multiply (GEMM) calculation unit. The SM includes a general-purpose register (GPR), and the GEMM calculation unit includes an instruction queue and a arithmetic logical unit (ALU). The ALU coupled to the GPR is arranged operably to perform MMA calculation according to a GEMM instruction stored in the instruction queue, and store a calculation result in the GPR.


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Hong, Zhou. (2023). Apparatus and method for vector computing incorporating with matrix multiply and accumulation calculation (U.S. Patent No. 11809516). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11809516

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