The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2023
Filed:
Apr. 16, 2021
Applicant:
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Inventors:
Neil Whyte, Edinburgh, GB;
Michael Chandler-Page, Stonehouse, GB;
Pradeep Saminathan, Edinburgh, GB;
Jon Eklund, Austin, TX (US);
Assignee:
Cirrus Logic Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 3/16 (2006.01); G06F 9/4401 (2018.01); G06F 21/60 (2013.01); G06F 21/62 (2013.01); G06F 21/74 (2013.01); G06F 21/85 (2013.01); G06F 21/76 (2013.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1441 (2013.01); G06F 13/1668 (2013.01); G06F 2212/1052 (2013.01);
Abstract
An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.