The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Aug. 06, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Hyun Tae Kim, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/10 (2016.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G11C 11/56 (2013.01); G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G06F 2212/657 (2013.01);
Abstract

The present technology includes a host configured to output a program request, a logical address, and data during a program operation, and a memory system configured to map a first physical address to the logical address, program the data to first memory blocks corresponding to the first physical address in a single level cell (SLC) method, program the data stored in the first memory blocks to a second memory block in a higher level cell method including a multi-level cell (MLC) method, a triple level cell (TLC) method, or a quadruple level cell (QLC) method after changing the first physical address to a second physical address, and transmit the second physical address to the host. The host outputs a read request and the second physical address to the memory system during a read operation of the data corresponding to the logical address.


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