The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Sep. 08, 2021
Applicant:

Shanghai Biren Technology Co., Ltd, Shanghai, CN;

Inventors:

Zhou Hong, Shanghai, CN;

Qin Zheng, Shanghai, CN;

ChengPing Luo, Shanghai, CN;

GuoFang Jiao, Shanghai, CN;

Song Zhao, Shanghai, CN;

XiangLiang Yu, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 12/02 (2006.01); G06F 13/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0615 (2013.01); G06F 12/0284 (2013.01); G06F 12/0646 (2013.01); G06F 13/124 (2013.01); G06F 2213/0026 (2013.01);
Abstract

An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.


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