The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Mar. 03, 2021
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Hiroyuki Abe, Tokyo, JP;

Kazune Matsumura, Tokyo, JP;

Gen Koide, Tokyo, JP;

Kentaro Agata, Tokyo, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1333 (2006.01); G02F 1/1362 (2006.01); G02F 1/1345 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G02F 1/133337 (2021.01); G02F 1/1345 (2013.01); G02F 1/13629 (2021.01); G02F 1/136209 (2013.01); G02F 1/13338 (2013.01); G02F 1/13685 (2021.01); G02F 1/134363 (2013.01); G02F 2201/56 (2013.01);
Abstract

A display device includes a substrate, a display region in which a plurality of pixels are provided on the substrate and that has a first side, a second side, a third side, a fourth side, and a plurality of curved portions, a peripheral region located between an end portion of the substrate and the display region, a plurality of scan lines extending in a first direction, a plurality of signal lines extending in a second direction, at least one gate driver arranged in the peripheral region and coupled to the scan lines, a signal line coupling circuit arranged in the peripheral region and coupled to the signal lines, a plurality of terminals aligned in the peripheral region, and a plurality of wiring lines coupling the terminals and the signal line coupling circuit.


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