The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Feb. 15, 2022
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Dmitry Pikulin, Vancouver, CA;

Mason L Thomas, Santa Barbara, CA (US);

Chetan Vasudeo Nayak, Santa Barbara, CA (US);

Roman Mykolayovych Lutchyn, Santa Barbara, CA (US);

Bas Nijholt, Delft, NL;

Bernard Van Heck, Rotterdam, NL;

Esteban Adrian Martinez, Copenhagen, DK;

Georg Wolfgang Winkler, Santa Barbara, CA (US);

Gijsbertus De Lange, Zoetermeer, NL;

John David Watson, Delft, NL;

Sebastian Heedt, Breda, NL;

Torsten Karzig, Goleta, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 27/28 (2006.01); G01R 27/02 (2006.01); G06N 10/20 (2022.01); G01R 27/32 (2006.01); G01R 35/00 (2006.01); H10N 60/12 (2023.01); H10N 69/00 (2023.01); G01R 27/04 (2006.01); G01R 27/16 (2006.01);
U.S. Cl.
CPC ...
G01R 27/02 (2013.01); G01R 27/28 (2013.01); G01R 27/32 (2013.01); G01R 35/005 (2013.01); G06N 10/20 (2022.01); G01R 27/04 (2013.01); G01R 27/16 (2013.01); H10N 60/12 (2023.02); H10N 69/00 (2023.02);
Abstract

A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.


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