The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Jan. 20, 2022
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

John Paul Strachan, Milpitas, CA (US);

Can Li, Houston, TX (US);

Catherine Graves, Milpitas, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/15 (2006.01); G11C 13/00 (2006.01); H03M 13/11 (2006.01); G11C 27/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/6597 (2013.01); G11C 13/004 (2013.01); H03M 13/1575 (2013.01); G11C 13/0069 (2013.01); G11C 27/005 (2013.01); H03M 13/1177 (2013.01);
Abstract

An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.


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