The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2023
Filed:
Mar. 06, 2020
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Jauwen Chen, Cupertino, CA (US);
Sunitha Venkataraman, San Jose, CA (US);
Ting Ku, San Jose, CA (US);
Assignee:
NVIDIA CORP., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H01L 27/0255 (2013.01); H01L 27/0277 (2013.01); H01L 27/0281 (2013.01);
Abstract
An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.