The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2023
Filed:
Aug. 25, 2021
Applicant:
Rohm Co., Ltd., Kyoto, JP;
Inventors:
Yuki Nakano, Kyoto, JP;
Ryota Nakamura, Kyoto, JP;
Assignee:
ROHM CO., LTD., Kyoto, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/04 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/046 (2013.01); H01L 21/0485 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/4236 (2013.01); H01L 29/42368 (2013.01); H01L 29/45 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01); H01L 29/7803 (2013.01); H01L 29/7805 (2013.01); H01L 29/0696 (2013.01); H01L 29/41766 (2013.01);
Abstract
A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.