The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Nov. 23, 2021
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Ikue Mitsuhashi, Kanagawa, JP;

Reijiroh Shohji, Tokyo, JP;

Minoru Ishida, Tokyo, JP;

Tadashi Iijima, Kanagawa, JP;

Takatoshi Kameshima, Kanagawa, JP;

Hideto Hashiguchi, Kanagawa, JP;

Hiroshi Horikoshi, Tokyo, JP;

Masaki Haneda, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14634 (2013.01); H01L 24/08 (2013.01); H01L 27/14636 (2013.01); H01L 2224/08145 (2013.01);
Abstract

A solid-state imaging device including a first substrate having a pixel unit formed thereon and including a first semiconductor substrate and a first multi-layered wiring layer stacked, a second substrate having a circuit formed thereon and including a second semiconductor substrate and a second multi-layered wiring layer, the circuit having a predetermined function, and a third substrate having a circuit formed thereon and including a third semiconductor substrate and a third multi-layered wiring layer. The first substrate and the second substrate are bonded together such that that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other. The solid-state imaging device includes a first coupling structure and a second coupling structure. The first coupling structure electrically couples a circuit of the first substrate and the circuit of the second substrate.


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