The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Mar. 03, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Keiichi Niwa, Yokkaichi Mie, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/29 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 24/30 (2013.01); H01L 21/563 (2013.01); H01L 23/293 (2013.01); H01L 23/3135 (2013.01); H01L 23/5383 (2013.01); H01L 24/13 (2013.01); H01L 24/27 (2013.01); H01L 25/18 (2013.01); H01L 2224/1357 (2013.01); H01L 2224/1369 (2013.01); H01L 2224/13551 (2013.01); H01L 2224/27515 (2013.01); H01L 2224/3003 (2013.01); H01L 2224/30104 (2013.01); H01L 2224/30515 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01);
Abstract

A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.


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