The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Oct. 14, 2021
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Chao-Wen Lay, Miaoli County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 21/768 (2006.01); G11C 5/06 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76837 (2013.01); G11C 5/063 (2013.01); H01L 21/76828 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H10B 12/482 (2023.02);
Abstract

A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.


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