The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

May. 04, 2022
Applicants:

Alexander Louis Braun, Baltimore, MD (US);

Max E. Nielsen, Riverton, UT (US);

Daniel George Dosch, Glen Burnie, MD (US);

Kurt Pleim, Halethorpe, MD (US);

Haitao O. Dai, Ellicott City, MD (US);

Charles Ryan Wallace, Orlando, FL (US);

Inventors:

Alexander Louis Braun, Baltimore, MD (US);

Max E. Nielsen, Riverton, UT (US);

Daniel George Dosch, Glen Burnie, MD (US);

Kurt Pleim, Halethorpe, MD (US);

Haitao O. Dai, Ellicott City, MD (US);

Charles Ryan Wallace, Orlando, FL (US);

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/32 (2006.01); H03L 7/081 (2006.01); H03K 3/037 (2006.01); H03K 19/195 (2006.01); H03L 7/08 (2006.01); H03K 3/38 (2006.01);
U.S. Cl.
CPC ...
G11C 19/32 (2013.01); H03K 3/037 (2013.01); H03K 3/38 (2013.01); H03K 19/195 (2013.01); H03L 7/0805 (2013.01); H03L 7/0816 (2013.01);
Abstract

Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.


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