The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Mar. 22, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Zachary Blair, San Jose, CA (US);

Alireza Kaviani, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/323 (2020.01); H01L 25/065 (2023.01); H01L 27/02 (2006.01); G06F 30/3947 (2020.01);
U.S. Cl.
CPC ...
G06F 30/323 (2020.01); G06F 30/3947 (2020.01); H01L 25/0655 (2013.01); H01L 27/0207 (2013.01);
Abstract

The embodiments herein rely on cross reticle wires (also referred to as cross die wires) to provide communication channels between programmable dies already formed on a wafer. Using cross reticle wires to facilitate x-die communication can be three to four orders of magnitude faster than using general purpose I/O. With a wafer containing cross reticle wires, various device geometries can be generated at dicing time by cutting across different reticle boundaries. This allows up to full wafer-size devices, or several smaller sub-wafer devices to be derived from one wafer. Although the programmable dies can contain defects, these defects can be identified and avoided when generating a bitstream for configuring programmable features in the programmable dies.


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