The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Apr. 23, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Xiaodong Meng, Hong Kong, HK;

Fan Yang, Singapore, SG;

Yufei Pan, Singapore, SG;

Hua Guan, San Diego, CA (US);

Kuan Chuang Koay, Singapore, SG;

Jize Jiang, Singapore, SG;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/59 (2006.01); G05F 1/575 (2006.01); H04B 1/40 (2015.01);
U.S. Cl.
CPC ...
G05F 1/59 (2013.01); G05F 1/575 (2013.01); H04B 1/40 (2013.01);
Abstract

The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.


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