The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2023
Filed:
Jul. 22, 2022
Dell Products, L.p., Round Rock, TX (US);
Bhavesh Govindbhai Patel, Austin, TX (US);
Arun Chada, Pflugerville, TX (US);
Bhyrav M. Mutnury, Austin, TX (US);
Dell Products, L.P., Round Rock, TX (US);
Abstract
Methods and systems are provided for designing an optimized stack up of layers of a PCB (Printed Circuit Board). A set of constraints is determined for the PCB stack up, where the constraints limit a total number of layers, a number of signal layers, and a thickness of the PCB stack up. Each of the constraints on the PCB stack up is encoded as an equality or an inequality. The set of equalities and inequalities is solved using integer programming techniques to identify an optimal solution to the set of constraints on the PCB stack up, where the optimal solution specifies an arrangement of signaling layers for the PCB. An estimate is generated for impedances and losses for the optimal PCB stack up. The constraints on a PCB stack up are modified when the estimated impedances and losses for the optimal PCB stack up are above a target threshold.