The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Apr. 07, 2020
Applicant:

University of Florida Research Foundation, Incorporated, Gainesville, FL (US);

Inventors:

Fatemeh Ganji, Gainesville, FL (US);

Shahin Tajik, Gainesville, FL (US);

Jean-Pierre Seifert, Werder Havel, DE;

Domenic Forte, Gainesville, FL (US);

Mark M. Tehranipoor, Gainesville, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/00 (2022.01); H04L 9/32 (2006.01); H04L 9/08 (2006.01); H03K 19/173 (2006.01); H03K 19/096 (2006.01); H03K 19/17748 (2020.01);
U.S. Cl.
CPC ...
H04L 9/3278 (2013.01); H03K 19/0963 (2013.01); H03K 19/1737 (2013.01); H03K 19/17748 (2013.01); H04L 9/002 (2013.01); H04L 9/0866 (2013.01); H04L 9/3271 (2013.01);
Abstract

Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.


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