The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Mar. 11, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young O Lee, Hwaseong-si, KR;

Min Su Kim, Hwaseong-si, KR;

Jeong Jin Lee, Hwaseong-si, KR;

Won Hyun Choi, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 3/017 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); H03K 3/012 (2013.01); H03K 3/017 (2013.01);
Abstract

A pulse-based flip flop circuit includes a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving either a data signal or the scan input signal responsive to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes a direct path providing a clock signal as a direct path input to a NAND circuit; a delay path including a number of plural stages that delay the clock signal and provide a delayed clock signal as a delay path input to the NAND circuit that performs a NAND operation on the direct path and delay path inputs to generate the inverted pulse signal; and a feedback path providing the pulse signal to a first stage among the stages of the delay path.


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