The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Nov. 30, 2021
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Johnny Klarenbeek, Austin, TX (US);

David P. Singleton, Edinburgh, GB;

Morgan T. Prior, Dunbar, GB;

Jonathan T. Wigner, Edinburgh, GB;

Christopher M. Dougherty, Austin, TX (US);

Qi Cai, Austin, TX (US);

Anindya Bhattacharya, Austin, TX (US);

Assignee:

Cirrus Logic Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 3/217 (2006.01); H03F 3/38 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0233 (2013.01); H03F 3/217 (2013.01); H03F 2200/03 (2013.01); H03F 2200/105 (2013.01);
Abstract

Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.


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