The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Jun. 30, 2021
Applicant:

Delta Electronics, Inc., Taipei, TW;

Inventors:

Chi Zhang, Apex, NC (US);

Zhiyu Shen, Cary, NC (US);

Ruxi Wang, Cary, NC (US);

Peter Mantovanelli Barbosa, Cary, NC (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 1/00 (2006.01); H02M 3/00 (2006.01); H02M 3/335 (2006.01);
U.S. Cl.
CPC ...
H02M 1/0074 (2021.05); H02M 3/01 (2021.05); H02M 3/33571 (2021.05); H02M 3/33592 (2013.01); H02M 1/0058 (2021.05); H02M 3/33573 (2021.05);
Abstract

The present disclosure provides a series resonant converter and its corresponding control method. In one aspect, the series resonant converter includes m (m=1,2,3, . . . ) sets of primary side stages in parallel, wherein each primary side stage is identical and includes n (n=2,3, . . . ) stacked element circuits, where the primary side stages receive an input voltage; n×m resonant networks coupled to the primary side stages; n×m transformers having n×m primary side windings and n×m secondary side windings, where the primary side windings are coupled to the n×m resonant networks; p (p=1,2,3, . . . ) sets of secondary side stages in parallel, wherein each secondary side stage is identical and includes q (q=n×m/p) stacked element circuits, where the secondary side stages are coupled to n×m secondary side windings; and a control block controlling the primary side switches according to the output voltage, input voltage and input capacitor voltages.


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