The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Apr. 04, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Munhyeon Kim, Hwaseong-si, KR;

Soonmoon Jung, Seongnam-si, KR;

Daewon Ha, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/08 (2006.01); H01L 21/84 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/84 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/42356 (2013.01); H01L 29/42368 (2013.01);
Abstract

A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.


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