The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Nov. 23, 2021
Applicant:

Coolcad Electronics, Llc, College Park, MD (US);

Inventors:

Neil Goldsman, Takoma Park, MD (US);

Akin Akturk, Gaithersburg, MD (US);

Zeynep Dilli, Rockville, MD (US);

Mitchell Adrian Gross, Baltimore, MD (US);

Usama Khalid, Hanover, MD (US);

Christopher James Darmody, Laurel, MD (US);

Assignee:

CoolCAD Electronics, LLC, College Park, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/16 (2006.01); H01L 21/82 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/8213 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7823 (2013.01);
Abstract

A SiC integrated circuit structure which allows multiple power MOSFETs or LDMOSs to exist in the same piece of semiconductor substrate and still function as individual devices which form the components of a given circuit architecture, for example, and not by limitation, in a half-bridge module. In one example, a deep isolation trench is etched into the silicon carbide substrate surrounding each individual LDMOS device. The trench is filled with an insulating material. The depth of the trench may be deeper than the thickness of an epitaxial layer to ensure electrical isolation between the individual epitaxial layer regions housing the individual LDMOSs. The width of the trench may be selected to withstand the potential difference between the bias levels of the body regions of neighboring power LDMOS devices.


Find Patent Forward Citations

Loading…