The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2023
Filed:
Dec. 16, 2021
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Shuo Zhang, Shenzhen, CN;
Eric Zhu, Shenzhen, CN;
Minto Zheng, Shenzhen, CN;
Michael Zhai, Chengdu, CN;
Town Zhang, Jiujiang, CN;
Jie Ma, Shenzhen, CN;
Assignee:
NVIDIA CORP., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 25/16 (2023.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/5386 (2013.01); H01L 25/16 (2013.01); H05K 1/181 (2013.01); H01L 2225/107 (2013.01); H01L 2225/1094 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10522 (2013.01); H05K 2201/10545 (2013.01); H05K 2201/10704 (2013.01);
Abstract
Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.