The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2023
Filed:
Jun. 22, 2021
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Eunseok Cho, Asan-si, KR;
Minjeong Gu, Asan-si, KR;
Joonsung Kim, Suwon-si, KR;
Jaehoon Choi, Seoul, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/552 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 25/065 (2023.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/4871 (2013.01); H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/552 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1616 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/30111 (2013.01);
Abstract
A semiconductor package includes a base substrate including a wiring pattern, an interposer substrate including lower and upper redistribution patterns, a semiconductor structure, a heat dissipation structure, a plurality of external connection bumps disposed on a lower surface of the base substrate, a plurality of lower connection bumps disposed between the base substrate and the interposer substrate, and a plurality of upper connection bumps disposed between the interposer substrate and the semiconductor structure.