The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

May. 30, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Junghoon Kang, Anyang-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01); H01L 25/00 (2006.01); H01L 21/683 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 21/4853 (2013.01); H01L 21/6835 (2013.01); H01L 23/5383 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 23/49811 (2013.01); H01L 2221/68381 (2013.01);
Abstract

A semiconductor package includes an interposer having a separation layer on a rear surface of which a plurality of first recesses is arranged. A plurality of wiring structures is stacked on the separation layer alternately with a plurality of insulation interlayers. A plurality of semiconductor devices is arranged, side by side, on the interposer side and connected to a plurality of the wiring structures. A plurality of contact terminals on the rear surface of the separation layer is connected to the plurality of the wiring structures through the separation layer. A flatness deterioration of the interposer is minimized and the contact surface between the interposer and under fill resin is enlarged.


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