The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Oct. 24, 2020
Applicant:

Hyperion Core, Inc., Los Gatos, CA (US);

Inventor:

Martin Vorbach, Lingenfeld, DE;

Assignee:

Hyperion Core, Inc., Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/78 (2006.01); G06F 9/30 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 12/0893 (2016.01); G11C 8/16 (2006.01); G11C 11/412 (2006.01); G06F 8/41 (2018.01); G06F 12/0877 (2016.01);
U.S. Cl.
CPC ...
G06F 15/7839 (2013.01); G06F 9/3017 (2013.01); G06F 9/30043 (2013.01); G06F 9/345 (2013.01); G06F 9/38 (2013.01); G06F 12/0893 (2013.01); G06F 15/7821 (2013.01); G06F 8/4441 (2013.01); G06F 8/452 (2013.01); G06F 12/0877 (2013.01); G06F 2212/2515 (2013.01); G06F 2212/282 (2013.01); G06F 2213/0038 (2013.01); G11C 8/16 (2013.01); G11C 11/412 (2013.01); Y02D 10/00 (2018.01);
Abstract

Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.


Find Patent Forward Citations

Loading…