The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Nov. 22, 2021
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Graeme Leslie Ingram, Melbourn, GB;

Michael Andrew Campbell, Waterbeach, GB;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0871 (2016.01); G06F 12/02 (2006.01); G06F 12/0808 (2016.01); G06F 12/0877 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0871 (2013.01); G06F 12/0246 (2013.01); G06F 12/0808 (2013.01); G06F 12/0877 (2013.01);
Abstract

The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface. A given access request considered by the cache control circuitry is provided with associated cache hint information providing one or more usage indications for given data at the memory address indicated by that given access request, and the cache control circuitry is arranged to reference the associated cache hint information when applying the power consumption based allocation policy to determine whether to cache the given data in the cache storage.


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