The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Oct. 01, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junghyun Roh, Asan-si, KR;

Minjae Lee, Suwon-si, KR;

Unho Cha, Asan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2020.01); H01L 23/50 (2006.01); H01L 23/552 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2607 (2013.01); H01L 23/50 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/552 (2013.01);
Abstract

A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop passing through the left-bottom corner region, a second conduction loop passing through the right-bottom corner region, a third conduction loop passing through the left-bottom corner region and the left-upper corner region, a fourth conduction loop passing through the right-bottom corner region and the right-upper corner region, and a shielding loop to shield electrical interference between the first through fourth conduction loops. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.


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