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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11791321 B1

PDFFull Text
Date of Patent:
Oct. 17, 2023

Filed:

Jan. 20, 2022

Method of fabricating semiconductor package and semiconductor package

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Tae-Young Lee, Bupyeong-gu, KR;

Dongok Kwak, Hwaseong-si, KR;

Boseong Kim, Bundang-gu, KR;

Sang Sub Song, Suwon-si, KR;

Joonyoung Oh, Bundang-gu, KR;

Assignee:

Samsung Electronics Co., Ltd.;

Attorney:

Fish & Richardson P.C.

Primary Examiner:

Jack S Chen

Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 23/552 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1052 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/3025 (2013.01);
Abstract

A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

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