The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Nov. 30, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Byungil Kim, Hwaseong-si, KR;

Yangwook Kim, Seoul, KR;

Pansoo Kim, Yongin-si, KR;

Hyeongtae Kim, Seoul, KR;

Sukyun Woo, Hwaseong-si, KR;

Jisu Yoon, Hwaseong-si, KR;

Hyunji Yoon, Daegu, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2016.01); G09G 3/34 (2006.01);
U.S. Cl.
CPC ...
G09G 3/32 (2013.01); G09G 3/3426 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0257 (2013.01); G09G 2320/064 (2013.01); G09G 2320/066 (2013.01); G09G 2320/0633 (2013.01);
Abstract

A display device may include: a light-emitting diode (LED) backlight unit (BLU), a pixel driving circuit configured to generate a scan signal and an image signal, a pixel circuit configured to generate an output current based on the scan signal and the image signal, and transmit the output current to the LED BLU, the pixel circuit including, a first transistor connected between an input pin and a node, the input pin configured to receive the image signal, the first transistor including a gate terminal configured to receive the scan signal, a second transistor connected between the node and a ground terminal, the second transistor including a gate terminal connected to the node, a third transistor connected between the node and a gate node, a fourth transistor configured to generate the output current according to a voltage of the gate node, and a capacitor connected to the gate node.


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