The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Feb. 15, 2022
Applicant:

Glenfly Tech Co., Ltd., Shanghai, CN;

Inventors:

Wenlin Hao, Shanghai, CN;

Fengxia Wu, Shanghai, CN;

Assignee:

Glenfly Tech Co., Ltd., Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 15/00 (2011.01); G06T 1/60 (2006.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06T 15/005 (2013.01); G06T 1/60 (2013.01); G06T 1/20 (2013.01);
Abstract

The present disclosure relates to a data process apparatus and a method thereof. The data process apparatus includes an internal memory unit and a shader level-1 cache. The internal memory unit is configured to store a to-be-cached matrix. The to-be-cached matrix includes at least a first element and a second element. The first element and the second element are stored in the internal memory unit in order of elements. The first element is located in a first row of the to-be-cached matrix, and the second element is located in next row of the to-be-cached matrix adjacent to the first row. The shader level-1 cache is connected to the internal memory unit, and configured to acquire the to-be-cached matrix to obtain a to-be-processed matrix stored in order of elements, and store the to-be-processed matrix. The data process apparatus can improve the efficiency of accessing the internal memory unit and reduce the bandwidth occupied by invalid data; enable hardware pipelines to be tighter and reduce idle clock cycles; and enable the shader level-1 cache to be smaller, thereby reducing hardware costs.


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