The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2023
Filed:
Jun. 02, 2021
Applicant:
Massachusetts Institute of Technology, Cambridge, MA (US);
Inventors:
Gage Krieger Hills, Mill Valley, CA (US);
Max Shulaker, Weston, MA (US);
Assignee:
Massachusetts Institute of Technology, Cambridge, MA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/337 (2020.01); G06F 111/04 (2020.01); G06F 119/10 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/337 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2119/02 (2020.01); G06F 2119/10 (2020.01);
Abstract
System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.