The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Jan. 29, 2020
Applicant:

Hitachi Astemo, Ltd., Hitachinaka, JP;

Inventors:

Taisuke Ueta, Tokyo, JP;

Tatsuya Horiguchi, Tokyo, JP;

Kenichi Shimbo, Tokyo, JP;

Hideyuki Sakamoto, Hitachinaka, JP;

Assignee:

Hitachi Astemo, Ltd., Hitachinaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 9/445 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/345 (2013.01); G06F 9/3877 (2013.01); G06F 9/44505 (2013.01);
Abstract

An electronic control device includes a processing control unit and an information acquisition unit. The information acquisition unit collects and transfers external environment information to the processing control unit, the processing control unit includes a first processor, a second processor, and a storage unit, the processing control unit executes arithmetic processing by a non-redundant and redundant processing configuration that executes non-redundant and redundant processing using the first processor and the second processor, respectfully, and the processing control unit stores a result of arithmetic processing by the non-redundant processing configuration in the storage unit, individually performs arithmetic processing using the stored result in both the first processor and the second processor by arithmetic processing by the redundant processing configuration, and performs determination for an arithmetic processing result by the non-redundant processing configuration based on an arithmetic result by the first processor and an arithmetic result by the second processor.


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